/*
 *  Copyright (c) 2022 ZhuHai Jieli Technology Co.,Ltd.
 *  Licensed under the Apache License, Version 2.0 (the "License");
 *  you may not use this file except in compliance with the License.
 *  You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 *  Unless required by applicable law or agreed to in writing, software
 *  distributed under the License is distributed on an "AS IS" BASIS,
 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *  See the License for the specific language governing permissions and
 *  limitations under the License.
 */

#ifndef ADAPTER_CPU_H
#define ADAPTER_CPU_H

#include "os/os_cpu.h"

#define TRIGGER         __asm__ volatile ("trigger")
#define SYNC            __asm__ volatile ("csync")

#define MULU(Rm, Rn)
#define MUL(Rm, Rn)
#define MLA(Rm, Rn)
#define MLUA(Rm, Rn)
#define MACCLR()
#define MACCSDIV()
#define MACCUDIV()
#define MLA0(Rm, Rn) MUL(Rm, Rn)
#define MLS(Rm, Rn)
#define MLS0(Rm, Rn) MUL(-Rm, Rn)
#define MRSIS(Rm, Rn)
#define MRSRS(Rm, Rn)
#define MRSI(Rm, Rn)
#define MRSR(Rm, Rn)
#define MACSET(h, l)
#define MACRL(l)
#define MACRH(l)
#define MULSIS(Ro, Rm, Rn, Rp) MUL(Rm, Rn); MRSIS(Ro, Rp)
#define MULSRS(Ro, Rm, Rn, Rp) MUL(Rm, Rn); MRSRS(Ro, Rp)

#endif
